Por favor, use este identificador para citar o enlazar a este item:
Compartir / Impacto:
|Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL|
High-Performance scientific computing on FPGA aboard the SOLAR ORBITER PHI instrument
|Autor:||Cobos Carrascosa, Juan Pedro|
|Director:||López Jiménez, A. C. ; Morillas Gutiérrez, Christian A.|
Arquitectura de ordenadores
Ciencias del espacio
|Fecha de publicación:||5-feb-2016|
|Editor:||Universidad de Granada|
CSIC - Instituto de Astrofísica de Andalucía (IAA)
|Resumen:||SO/PHI (Solar Orbiter Polarimetric and Helioseismic Imager) is a filtergraph-based, solar magnetograph aimed at mapping the vector magnetic field and the line-of-sight (LOS) velocity of the solar photospheric plasma. It belongs to the scientific payload of the European Space Agency’s Solar Orbiter mission which will orbit the Sun at 0.28 astronomical units.
The limited telemetry rate combined with the large amount of scientific information retrieved by the SO/PHI instrument demand a sophisticated on-board data reduction and scientific analysis through the study of the polarization state of a specific spectral line. The main aim is to perform the complicated algorithm needed to translate the polarization state of the light spectrum in terms of some specific solar parameters like the magnetic field vector and velocity. Technically speaking, the inference of the solar physical quantities through a spectropolarimetric study is based on the inversion of the Radiative Transfer Equation (RTE) and these tasks require the processing of a huge quantity of data in parallel.|
The RTE inverter is the core of the on-board scientific data analysis and, probably, one of the most innovative parts of the instrument. Due to the unavailability of qualified for space processors, DSPs, or GPGPUs that fulfil the stringent computational requirements with the limited room and power consumption allocated to the instrument, a specifically designed hardware device has been implemented in SO/PHI. This device is in charge of inverting the RTE aboard Solar Orbiter under narrow time and power constraints. The main aim of this thesis is to design, build, and test such a hardware device for SO/PHI. With that goal in mind, we propose two different high-performance computing architectures for carrying out the RTE inversion using FPGA devices embedded in the SO/PHI instrument. The first of these proposals is a distributed-memory MIMD multiprocessor architecture on a Virtex-5 FPGA that exploits the functional and data fine parallelism. It uses a pipelined execution based on a novel MIMD programming method. The processors within the architecture are simplified for saving resources but they are able of eliminating latency and exploiting the computing power that the FPGA provides. The synchronization and the communication network between processors have been simplified using this proposal. The second proposal consists of a SIMD multiprocessor architecture to reach high performance in floating point operations. This architecture on a Virtex-4 FPGA squeezes the FPGA resources in order to reach the time constraints. It is focused in exploiting the data parallelism using several processors working together and using different data streams. One of the most important contributions of this architecture is the ability of saving resources allocating operation cores in a shared operation block, which is accessed by every processor. Some details for extending the architecture to other problems are pointed out. A study of how the radiation induced errors affect each block of the architecture is detailed, and two fault mitigation strategies are described. We also present a novel software tool, which automates the entire design process and system settings from an input C-like pseudo-code. This tool uses advanced techniques of software pipelining and parallelizing scientific algorithms in multicore systems. A compiler within the tool makes it easier the use and programming of the proposed MIMD and SIMD architectures. As a byproduct of our development, a specific, novel Singular Value Decomposition (SVD) architecture within the SIMD architecture is proposed as well. SVD is one of the steps in the RTE inversion but can be of interest to other developments as is a fairly common mathematical tool. The achieved FPGA systems improve the time and power consumption of ground-based systems based on commercial CPUs. The final system is tested using synthetic and real data. It satisfies the scientific precision requirements and the engineering computing time and power consumption requirements.
|Descripción:||Tesis Universidad de Granada. Programa Oficial de Posgrado Ciencias de la Computación y Tecnología Informática|
|Aparece en las colecciones:||(IAA) Tesis|
Ficheros en este ítem:
|thesis_JuanP_Cobos.pdf||Tesis_IAA_Cobos_Carrascosa.pdf||16,06 MB||Adobe PDF|
Mostrar el registro completo
NOTA: Los ítems de Digital.CSIC están protegidos por copyright, con todos los derechos reservados, a menos que se indique lo contrario.