English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/136787
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:

Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links

AuthorsYousefzadeh, Amirreza; Plana, Luis A.; Temple,Steve; Serrano-Gotarredona, Teresa ; Furber, Steve B.; Linares-Barranco, Bernabé
Issue Date2016
PublisherInstitute of Electrical and Electronics Engineers
CitationIEEE Transactions on Circuits and Systems - II - Express Briefs, 63 (8): 763-767 (2016)
AbstractAsynchronous handshaken interchip links are very popular among neuromorphic full-custom chips due to their delay-insensitive and high-speed properties. Of special interest are those links that minimize bit-line transitions for power saving, such as the two-phase handshaken non-return-to-zero (NRZ) 2-of-7 protocol used in the SpiNNaker chips. Interfacing such custom chip links to field-programmable gate arrays (FPGAs) is always of great interest, so that additional functionalities can be experimented and exploited for producing more versatile systems. Present-day commercial FPGAs operate typically in synchronous mode, thus making it necessary to incorporate synchronizers when interfacing with asynchronous chips. This introduces extra latencies and precludes pipelining, deteriorating transmission speed, particularly when sending multisymbols per unit communication packet. In this brief, we present a technique that learns to estimate the delay of a symbol transaction, thus allowing a fast pipelining from symbol to symbol. The technique has been tested on links between FPGAs and SpiNNaker chips, achieving the same throughput as fully asynchronous synchronizerless links between SpiNNaker chips. The links have been tested for periods of over one week without any transaction failure. Verilog codes of FPGA circuits are available as additional material for download.
Publisher version (URL)http://dx.doi.org/10.1109/TCSII.2016.2531092
Appears in Collections:(IMSE-CNM) Artículos
Files in This Item:
File Description SizeFormat 
07410001.pdf1,08 MBAdobe PDFThumbnail
Show full item record
Review this work

Related articles:

WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.