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Título: | Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR |
Autor: | Morgado, Alonso CSIC ORCID; Río, Rocío del CSIC ORCID; Rosa, José M. de la CSIC ORCID | Fecha de publicación: | 2016 | Editor: | Institute of Electrical and Electronics Engineers | Citación: | IEEE International Symposium on Circuits and Systems (ISCAS) 2016 | Resumen: | This paper presents the design and implementation of a fourth-order band-pass continuous-time ΣΔ modulator intended for the digitization of radio-frequency signals in software-defined-radio applications. The modulator architecture consists of two Gm-LC resonators with a tunable notch frequency and a 4-bit flash analog-to-digital converter in the forward path and a non-return-to-zero digital-to-analog converter with a finite-impulse-response filter in the feedback path. Both system-level and circuit-level reconfiguration techniques are included in order to allow the modulator to digitize signals placed at different carrier frequencies, from 450MHz to 950MHz. A proper synthesis methodology of the loop-filter coefficients at system level and the use of inverter-based switchable transconductors allow to optimize the performance in terms of robustness to circuit errors, stability and power consumption. The circuit, implemented in 65-nm CMOS, can digitise signals with up to 57-dB SNDR within a 40-MHz bandwidth, with an adaptive power dissipation of 16.7-to-22.8 mW and a programmable 1.2/2GHz clock rate1. | Versión del editor: | http://dx.doi.org/10.1109/ISCAS.2016.7527168 | URI: | http://hdl.handle.net/10261/136535 | DOI: | 10.1109/ISCAS.2016.7527168 |
Aparece en las colecciones: | (IMSE-CNM) Comunicaciones congresos |
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Fichero | Descripción | Tamaño | Formato | |
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iscas2016_RFBPSDM_final.pdf | 2,41 MB | Adobe PDF | Visualizar/Abrir |
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