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Image Feature Extraction Acceleration

AutorFernández-Berni, J. ; Suárez, Manuel; Carmona-Galán, R. ; Brea, V. M.; Río, Rocío del; Cabello, D.; Rodríguez-Vázquez, Ángel
Palabras claveImage Feature Extraction
Focal-Plane Acceleration
Distributed Memory
Parallel Processing
Vision Chip
Fecha de publicación2016
CitaciónImage Feature Detectors and Descriptors. Ali Ismail Awad, M. Hassaballah, Eds. (2016)
ResumenImage feature extraction is instrumental for most of the best-performing algorithms in computer vision. However, it is also expensive in terms of computational and memory resources for embedded systems due to the need of dealing with individual pixels at the earliest processing levels. In this regard, conventional system architectures do not take advantage of potential exploitation of parallelism and distributed memory from the very beginning of the processing chain. Raw pixel values provided by the front-end image sensor are squeezed into a high-speed interface with the rest of system components. Only then, after deserializing this massive dataflow, parallelism, if any, is exploited. This chapter introduces a rather different approach from an architectural point of view. We present two Application-Specific Integrated Circuits (ASICs) where the 2-D array of photo-sensitive devices featured by regular imagers is combined with distributed memory supporting concurrent processing. Custom circuitry is added per pixel in order to accelerate image feature extraction right at the focal plane. Specifically, the proposed sensing-processing chips aim at the acceleration of two flagships algorithms within the computer vision community: the Viola-Jones face detection algorithm and the Scale Invariant Feature Transform (SIFT). Experimental results prove the feasibility and benefits of this architectural solution.
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