2024-03-29T13:38:54Zhttp://digital.csic.es/dspace-oai/requestoai:digital.csic.es:10261/833062021-10-28T14:39:22Zcom_10261_90com_10261_4col_10261_343
LC-VCO design optimization methodology based on the gm/ID ratio for nanometer CMOS technologies
Fiorelli, R.
Peralías, E.
Silveira, Fernando
El pdf del artículo es la versión pre-print.
In this paper, an LC voltage-controlled oscillator (LC-VCO) design optimization methodology based on the gm/ID technique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier. © 2011 IEEE.
This work was supported in part by the MOSIS Research Program, the Uruguayan projects PDT 69/08 and PDT 63/361; the bilateral cooperation projects CSIC-UR 2007UY0017 and 2009UY0019, and the Spanish Grant MAE-AECID.
Peer Reviewed
2013-10-04T10:25:21Z
2013-10-04T10:25:21Z
2011
2013-10-04T10:25:21Z
artículo
http://purl.org/coar/resource_type/c_6501
doi: 10.1109/TMTT.2011.2132735
issn: 0018-9480
IEEE Transactions on Microwave Theory and Techniques 59(7): 1822-1831 (2011)
http://hdl.handle.net/10261/83306
10.1109/TMTT.2011.2132735
en
http://dx.doi.org/10.1109/TMTT.2011.2132735
open
Institute of Electrical and Electronics Engineers