2024-03-29T01:33:46Zhttp://digital.csic.es/dspace-oai/requestoai:digital.csic.es:10261/851812017-07-05T10:01:56Zcom_10261_90com_10261_4col_10261_343
2013-10-28T12:25:03Z
urn:hdl:10261/85181
ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy
Liñán-Cembrano, G.
Espejo-Meana, S.
Domínguez-Castro, R.
Rodríguez-Vázquez, Ángel
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable analog parallel processing, and distributed image memory cache on a common silicon substrate. This chip, designed in a 0.5 μm standard CMOS technology contains around 1.000.000 transistors, of which operate in analog mode; it is hence one the most complex mixed-signal chip reported to now. Chip functional features are: local interactions, spatial-invariant array architecture; programmable local interactions among cells; randomly-selectable memory of instructions (elementary instructions are defined by specific values of the cell local interactions); random storage/retrieval of intermediate images; capability to complete algorithmic image processing tasks controlled by the user-selected stored instructions and interacting with the cache memory, etc. Thus, as illustrated in this paper, the chip is capable to complete complex spatio-temporal image processing tasks within short computation time (< 300 ns for linear convolutions) and using a low power budget (< 1.2 W for the complete chip). The internal circuitry of the chip has been designed to operate in robust manner with > 7-bits equivalent accuracy in the internal analog operations, which has been confirmed by experimental measurements. Such 7-bits accuracy is enough for most image processing applications. ACE4k has been demonstrated capable to implement up to 30 templateσ-either directly or through template decomposition. This means the 100% of the 3 × 3 linear templates reported in Roska et al. 1998, [1]. Copyright © 2002 John Wiley & Sons, Ltd.
2013-10-28T12:25:03Z
2013-10-28T12:25:03Z
2002
2013-10-28T12:25:03Z
artículo
International Journal of Circuit Theory and Applications 30(2-3): 89-116 (2002)
http://hdl.handle.net/10261/85181
10.1002/cta.191
eng
closedAccess
Wiley-Blackwell