Improved AER convolution chip for vision processing with higher resolution and new functionalities

Abstract

We present a new neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing system. This chip computes 2-D convolutions with a programmable kernel in real time. Previously, we designed and tested another convolution chip with a size of 32 x 32 pixels [1] and, based on the information obtained from this test, we have designed a new chip with larger resolution (64 x 64 pixels), improved behavior and new functionalities included. This chip receives and generates data in AER format, which is an asynchronous protocol, implementing the convolution of the input images with a programmable kernel. The most important new functionality included in this chip is the multikernel capability, which allows us to program several kernels (up to 32) so that each input event will be processed with the corresponding kernel, depending on the origin of the input event. The paper describes the architecture of the chip, with special emphasis to the new improvements.