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dc.contributor.authorGinés, A. J.-
dc.contributor.authorDoldán, R.-
dc.contributor.authorVillegas, A.-
dc.contributor.authorAcosta, Antonio José-
dc.contributor.authorJalón, M. A.-
dc.contributor.authorVázquez, Diego-
dc.contributor.authorRueda, Adoración-
dc.contributor.authorPeralías, E.-
dc.date.accessioned2013-11-15T11:43:12Z-
dc.date.available2013-11-15T11:43:12Z-
dc.date.issued2008-
dc.identifierdoi: 10.1109/APCCAS.2008.4746254-
dc.identifierisbn: 978-1-4244-2341-5-
dc.identifier.citationIEEE Asia Pacific Conference on Circuits and Systems: 1252-1255 (2008)-
dc.identifier.urihttp://hdl.handle.net/10261/86805-
dc.description.abstractA low-cost 1.2 V 5.14 mW phase-lock loop (PLL) quadrature frequency synthesizer compliant with the 2.4 GHz ZigBee standard (IEEE 802.15.4) has been implemented in 90 nm CMOS technology. In-phase and quadrature (I/Q) components exhibit a phase noise of -105.9 dBc/Hz at 1 MHz offset from the carrier. The PLL die area including decoupling capacitors and testing buffers is 209times422 mum2.-
dc.language.isoeng-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.rightsclosedAccess-
dc.titleA 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications-
dc.typeComunicación de congreso-
dc.identifier.doi10.1109/APCCAS.2008.4746254-
dc.date.updated2013-11-15T11:43:12Z-
dc.description.versionPeer Reviewed-
Appears in Collections:(IMSE-CNM) Libros y partes de libros
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