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Geometry optimization in basic CMOS cells for improved power, leakage, and noise performances

AuthorsCastro, Javier; Acosta, Antonio José ; Vesterbacka, M.
Issue Date2008
PublisherInstitute of Electrical and Electronics Engineers
CitationInternational Conference on Advances in Electronics and Micro-electronics: 48-53 (2008)
AbstractThe rising demand for portable system is increasing the importance of low power as a design consideration. In this sense, leakage power is increasing much faster than dynamic power at smaller dimensions. Peak values of supply current are related to noise injected into the substrate and/or propagated through supply network, limiting the performances of the sensitive analog and RF portions of mixed-signal circuits. This paper analyses how these three aspects, dynamic power, leakage power and peak power, can be considered together, optimizing the sizing and design of basic cells, with a reduced degradation in performances. The suited sizing of basic cells, show the benefits of the proposed technique, validated through simulation results on 130 nm nand, nor and inverter cells.
DescriptionComunicación presentada al "ENICS'08" celebrado en Valencia del 29 de Septiembre al 4 de Octubre de 2008.
Publisher version (URL)http://dx.doi.org/10.1109/ENICS.2008.26
Identifiersdoi: 10.1109/ENICS.2008.26
isbn: 978-0-7695-3370-4
Appears in Collections:(IMSE-CNM) Libros y partes de libros
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