English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/85850
Share/Impact:
Statistics
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:
Title

Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits

AuthorsAcosta, Antonio José ; Mora-Gutiérrez, J. M. ; Castro, Javier; Parra, P.
Issue Date2007
PublisherThe International Society for Optics and Photonics
CitationProceedings of SPIE 6590: 659007 (2007)
AbstractThe buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits and systems. The driver or repeater used to this purpose has effect on the timing characteristics on the signal on the wire, as propagation delay, signal integrity, transition time, among others. The power concerns related to buffering have also received much attention, because of the low power requirements of modern integrated systems. In the same way, the buffer insertion has strong impact on the reliability of synchronous systems, since the suited distribution of clock requires reduced or controlled clock-skew, being the buffer and wire sizing, a crucial aspect. In a different way, buffer insertion has been also used to reduce noise generation, especially in heavily loaded nets, since the inclusion of buffers help to desynchronize signal transitions. However, the inclusion of buffers of inverters to improve one or more of these characteristics have often negative effect on another parameters, as it happens in the average and peak of supply current. Mainly, the inclusion of a buffer to reduce noise (peak power), via desynchronizing transitions, could introduce more dynamic consumption, but reducing the short-circuit current because of the increment of signal slope. Thus, the average/peak current optimization can be considered a design trade-off. In this paper, the mechanism to obtain an average/peak power optimization procedure are presented. Selected examples show the feasibility of minimizing switching noise with negligible impact on average power consumption.
DescriptionTrabajo presentado al "VLSI Circuits and Systems III" celebrado en Maspalomas (España) en Mayo del 2007.
Publisher version (URL)http://dx.doi.org/10.1117/12.724162
URIhttp://hdl.handle.net/10261/85850
DOI10.1117/12.724162
E-ISSN0277-786X
Identifiersdoi: 10.1117/12.724162
issn: 1996-756X
Appears in Collections:(IMSE-CNM) Artículos
Files in This Item:
File Description SizeFormat 
Effects of buffer.pdf165,35 kBAdobe PDFThumbnail
View/Open
Show full item record
Review this work
 


WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.