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ACE16k: A programmable focal plane vision processor with 128 x 128 resolution

AutorLiñán-Cembrano, G. ; Domínguez-Castro, R. ; Espejo-Meana, S. ; Rodríguez-Vázquez, Ángel
Fecha de publicación2001
EditorEuropean Conference on Circuit Theory and Design
CitaciónEuropean Conference on Circuit Theory and Design: "Circuit Paradigm in the 21st Century" (2001)
ResumenThis paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system level perspective. The design has recently sent to fabrication in a 0.35μm standard digital 1P-5M CMOS Technology. The chip has been designed to achieve the high-speed and moderate-accuracy constraints of most real time image processing applications. It has been designed to be easily embedded in conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four millions transistors, 80% of them working in analog mode, and exhibits a relatively low power consumption (<4W, i.e. less than 1mW per transistor). Experimental results are expected for the date of paper presentation.
DescripciónComunicación presentada al "ECCTD’01" celebrada del 28 al 31 de Agosto del 2001 en Finlandia.
Versión del editorhttp://radio.tkk.fi/en/conferences/ecctd01/
URIhttp://hdl.handle.net/10261/85269
Aparece en las colecciones: (IMSE-CNM) Comunicaciones congresos
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