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Architectural and basic circuit considerations for a flexible 128 × 128 mixed-signal SIMD vision chip

AutorLiñán-Cembrano, G. ; Espejo-Meana, S. ; Domínguez-Castro, R. ; Rodríguez-Vázquez, Ángel
Fecha de publicación2002
CitaciónAnalog Integrated Circuits and Signal Processing 33(2): 179-190 (2002)
ResumenFrom a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35 μm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (∼7 bits) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330 GOPs (Giga Operations per second), and uses the power supply (180 GOP/Joule) and the silicon area (3.8 GOPS/mm2) efficiently, and is able to maintain VGA processing throughputs of 100 Frames/s with about 10-20 basic image processing tasks on each frame.
Identificadoresdoi: 10.1023/A:1021272100265
issn: 0925-1030
e-issn: 1573-1979
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