English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/84913
Share/Impact:
Statistics
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:
Title

Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure

AuthorsAcosta, Antonio José ; Barriga, Angel ; Bellido, M. J.; Valencia-Barrero, M. ; Huertas-Díaz, J. L.
Issue Date1998
PublisherInstitute of Electrical and Electronics Engineers
CitationIEE Proceedings Circuits, Devices and Systems 145(4): 247-253 (1998)
AbstractThe authors describe the design, integration and characterisation of a bit-level pipelined self-timed multiplier architecture. The differential structure SODS (switched-output differential structure) has been used for computation blocks and the PLCAR structure (protocol and latching controlled by acknowledge and request) for the interface blocks, introduced in an array-based architecture. A 4 x 4-bit multiplier has been integrated in a l.Oum CMOS technology and the proposed architecture has been compared with other asynchronous approaches, showing a considerable improvement, up to 50% in terms of area, speed and power consumption. Compared with a synchronous approach, the main advantage of the proposed architecture is a lower power consumption below a certain incoming input data rate, but at the expense of area and speed. © IEE, 1998.
URIhttp://hdl.handle.net/10261/84913
DOI10.1049/ip-cds:19982125
Identifiersdoi: 10.1049/ip-cds:19982125
issn: 1350-2409
Appears in Collections:(IMSE-CNM) Artículos
Files in This Item:
File Description SizeFormat 
accesoRestringido.pdf15,38 kBAdobe PDFThumbnail
View/Open
Show full item record
Review this work
 

Related articles:


WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.