English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/84888
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:

CMOS inverter maximum frequency of operation due to digital signal degradation

AuthorsJuan-Chico, J. ; Bellido, M. J.; Acosta, Antonio José ; Barriga, Angel ; Valencia-Barrero, M.
Issue Date1997
PublisherInstitute of Electrical and Electronics Engineers
CitationElectronics Letters 33(19): 1619-1621 (1997)
AbstractAn operation frequency limit for the CMOS inverter is presented, based on delay degradation. This allows treatment of the problem from a purely logical viewpoint. Classical calculations are shown to lead to large over-estimations.
Identifiersdoi: 10.1049/el:19971102
issn: 0013-5194
e-issn: 1350-911X
Appears in Collections:(IMSE-CNM) Artículos
Files in This Item:
File Description SizeFormat 
accesoRestringido.pdf15,38 kBAdobe PDFThumbnail
Show full item record
Review this work

Related articles:

WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.