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Design of a smart camera SoC in a 3D-IC technology

AuthorsCarmona-Galán, R. ; Fernández-Berni, J. ; Vargas-Sierra, S. ; Liñán-Cembrano, G. ; Rodríguez-Vázquez, Ángel ; Brea, V. M.; Suárez, Marta ; Cabello, D.
Issue Date2012
CitationWorkshop on Architecture of Smart Camera (2012)
AbstractConventional digital signal processing architectures introduce data bottlenecks and are inefficient when dealing with multidimensional sensory signals; Architectures adapted to the nature of the stimulus are more efficient in terms of power consumption per operation but...;Concurrent sensing, processing and memory in planar technologies introduces serious limitations to image resolution and image size via the penalties in fill factor and pixel pitch; 3D integrated circuit technologies with a dense TSV distribution permits eliminating data bottlenecks without degrading image resolution and size.
DescriptionTrabajo presentado al "WASC 2012" celebrado en Francia del 5 al 6 de Abril del 2012.
Appears in Collections:(IMSE-CNM) Comunicaciones congresos
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