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Título

A 3-D chip architecture for optical sensing and concurrent processing

AutorRodríguez-Vázquez, Ángel ; Carmona-Galán, R. ; Suárez, Marta ; Brea, V. M.; Pozas-Flores, F. ; Liñán-Cembrano, G. ; Zarandy, A.
Fecha de publicación2010
EditorSociety of Photo-Optical Instrumentation Engineers
CitaciónOptical Sensing and Detection (2010)
SerieProceedings of SPIE 7726
ResumenThis paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This architecture employs the multi-functional pixel concept to achieve full parallel processing of the information and hence high processing speed. The top layer includes an array of optical sensors which are parallel-connected to the second layer, consisting of an array of mixed-signal read-out and pre-processing cells. Multiplexing is employed so that each mixedsignal cell handles several optical sensors. The two remaining layer are respectively a memory (used to store different multi-scale images obtained at the mixed-signal layer) and an array of digital processors. A prototype of this architecture has been implemented in a FDSOI CMOS-3D technology with Through-Silicon-Vias of 5μm x 5μm pitch.
DescripciónComunicación presentada al "Optical Sensing and Detection" celebrado en Bruselas (Bélgica) del 12 al 15 de Abril del 2010.-- et al.
Versión del editorhttp://dx.doi.org/10.1117/12.855027
URIhttp://hdl.handle.net/10261/84630
DOI10.1117/12.855027
Identificadoresdoi: 10.1117/12.855027
isbn: 9780819481993
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