Baseband-processor for a passive UHF RFID transponder

Abstract

This paper describes the design of a digital processor targeting the Class-1 Generation-2 EPC Protocol for UHF RFID transponders, and proposes different techniques for reducing its power consumption. The processor has been implemented in a 0.35μm CMOS technology process using automatic tools for both the logic synthesis and layout. Post-layout simulations confirm the fully functionality of the prototype and predict a worst-case power consumption of only 2.9μA at 1.2V supply.