English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/84001
logo share SHARE   Add this article to your Mendeley library MendeleyBASE
Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:

A 0.2pJ/conversion-step 6-bit 200MHz flash ADC with redundancy

AuthorsDarwish, Hala; Léger, G. ; Rueda, Adoración
Issue Date2012
Citation27th Conference DCIS (2012)
AbstractIn this paper, a 200MHz 6-bit Flash analog-to-digital converter (ADC) is presented. The principal objective is to obtain a digital-friendly converter. Hence, small and simple latched comparators are used and redundancy allows reducing the offset down to an acceptable level. This obviously requires calibration but reduces power consumption, since small size transistors can be used and the unused comparators are powered down. The proposed ADC is designed in UMC 0:18m CMOS technology. Full electrical simulations show that the ADC reaches an effective number of bits (ENOB) of 5.3 associated to a signal-to-noise-anddistortion ratio (SNDR) is 33dB. The converter consumes only 1.56mW and has figure-of-merit (FoM) of 0.2 pJ / conversion step.
DescriptionComunicación presentada al "27th Conference on Design of Circuits and Integrated Systems (DCIS 2012)" celebrada del 28 al 30 de Noviembre del 2012 en Avignon (Francia), organizada por el LIRMM laboratory of Montpellier: http://www.lirmm.fr/dcis2012/index.php
Appears in Collections:(IMSE-CNM) Comunicaciones congresos
Files in This Item:
File Description SizeFormat 
200MHz flash ADC.pdf172,94 kBUnknownView/Open
Show full item record
Review this work

WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.