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A 0.2-to-2MHz BW, 50-to-86dB SNDR, 16-to-22mW Flexible 4th-Order ΣΔ modulator with DC-to-44MHz tunable center frequency in 1.2-V 90-nm CMOS

AutorAsghar, S. ; Río, Rocío del; Rosa, José M. de la
Fecha de publicación2012
EditorInstitute of Electrical and Electronics Engineers
CitaciónIEEE/IFIP 20th International Conference on VLSI and System-on-Chip: 47-52 (2012)
ResumenThis paper describes the design of a switched-capacitor fourth-order single-loop ΣΔ modulator with a 5-level embedded quantizer. The loop filter consists of a cascade of resonators with distributed feedforward coefficients, which can be programmed to make the zeros of the noise transfer function variable. As a result, the modulator can be reconfigured either as a lowpass or as a bandpass analog-to-digital converter with a tunable notch frequency and an optimized loop-filter zero placement. The circuit - designed and implemented in a 1.2-V 90-nm CMOS technology - incorporates diverse architecture- and circuit-level strategies to adapt its performance to different sets of specifications with a variable sampling frequency of 100 and 200MHz and scalable power consumption. Post-layout simulations (for a frequency range of DC to 22MHz) and behavioral simulations (from 22 to 44MHz) show a correct operation of the circuit in steps of 1-to-2MHz, featuring an adaptive SNDR of 74-to-86, 57-to-68 and 50-to-59dB within a signal bandwidth of 200kHz, 1MHz and 2MHz, respectively, while dissipating a scalable power consumption of 16-to-22mW*.
DescripciónTrabajo presentado al 20th VLSI-SoC celebrado en Sabta Cruz (CA) del 7 al 19 de octubre de 2012.
Versión del editorhttp://dx.doi.org/10.1109/VLSI-SoC.2012.6379004
URIhttp://hdl.handle.net/10261/83896
DOI10.1109/VLSI-SoC.2012.6379004
Identificadoresdoi: 10.1109/VLSI-SoC.2012.6379004
isbn: 978-1-4673-2657-5
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