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A 350 µW 2.3 GHz integer-N frequency synthesizer for body area network applications

AuthorsMasuch, Jens ; Delgado-Restituto, Manuel
Issue Date2011
PublisherInstitute of Electrical and Electronics Engineers
Citation11th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF): 105-108 (2011)
AbstractThis paper presents a low power integer-N synthesizer with an output frequency of 2.3 GHz. The complete PLL has been integrated in a 90 nm CMOS technology and operates from a 1 V supply voltage. The synthesizer has been optimized for power consumption by employing an efficient quadrature VCO and a phase-switching prescaler. It achieves a phase noise of -121 dBc/Hz @3MHz while consuming only 350 μW in the PLL core. The typical reference spur level is about -40 dBc.
DescriptionConferencia celebrada en Phoenix (EE.UU) del 17 al 19 de Enero del 2011.
Publisher version (URL)http://dx.doi.org/10.1109/SIRF.2011.5719342
Identifiersdoi: 10.1109/SIRF.2011.5719342
isbn: 978-1-4244-8060-9
Appears in Collections:(IMSE-CNM) Libros y partes de libros
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