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FLIP-Q: A QCIF resolution focal-plane array for low-power image processing

AuthorsFernández-Berni, J. ; Carmona-Galán, R. ; Carranza-González, L.
Issue DateMar-2011
PublisherInstitute of Electrical and Electronics Engineers
CitationIEEE Journal of Solid-State Circuits 46(3): 669-680 (2011)
AbstractThis paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35 CMOS-OPTO process. The chip implements a massively parallel focal-plane processing array which can output different simplified representations of the scene at very low power. The array is composed of pixel-level processing elements which carry out analog image processing concurrently with photosensing. These processing elements can be grouped into fully-programmable rectangular-shape areas by loading the appropriate interconnection patterns into the registers at the edge of the array. The targeted processing can be thus performed block-wise. Readout is done pixel-by-pixel in a random access fashion. On-chip 8b ADC is provided. The image processing primitives implemented by the chip, experimentally tested and fully functional, are scale space and Gaussian pyramid generation, fully-programmable multiresolution scene representation-including foveation-and block-wise energy-based scene representation. The power consumption associated to the capture, processing and A/D conversion of an image flow at 30 fps, with full-frame processing but reduced frame size output, ranges from 2.7 mW to 5.6 mW, depending on the operation to be performed.
DescriptionEl pdf del artículo es la versión pre-print.
Publisher version (URL)http://dx.doi.org/10.1109/JSSC.2010.2102591
Appears in Collections:(IMSE-CNM) Artículos
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