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Title

A 32, x, 32 pixel convolution processor chip for address event vision sensors with 155 ns event latency and 20 meps throughput

AuthorsCamuñas-Mesa, L. ; Acosta, Antonio José ; Zamarreño-Ramos, Carlos ; Serrano-Gotarredona, Teresa ; Linares-Barranco, Bernabé
Issue DateNov-2010
PublisherInstitute of Electrical and Electronics Engineers
CitationIEEE Transactions on Circuits and Systems I: Regular Papers 58(4): 777-790 (2010)
AbstractThis paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional frame-constraint vision systems, in event-driven vision there is no need for frames. In frame-free event-based vision, information is represented by a continuous flow of self-timed asynchronous events. Such events can be processed on the fly by event-based convolution chips, providing at their output a continuous event flow representing the 2-D filtered version of the input flow. In this paper we present a 32 × 32 pixel 2-D convolution event processor whose kernel can have arbitrary shape and size up to 32 × 32. Arrays of such chips can be assembled to process larger pixel arrays. Event latency between input and output event flows can be as low as 155 ns. Input event throughput can reach 20 Meps (mega events per second), and output peak event rate can reach 45 Meps. The chip can be configured to discriminate between two simulated propeller-like shapes rotating simultaneously in the field of view at a speed as high as 9400 rps (revolutions per second). Achieving this with a frame-constraint system would require a sensing and processing capability of about 100 K frames per second. The prototype chip has been built in 0.35 CMOS technology, occupies 4.3 × 5.4 and consumes a peak power of 200 mW at maximum kernel size at maximum input event rate.
Publisher version (URL)http://dx.doi.org/10.1109/TCSI.2010.2078851
URIhttp://hdl.handle.net/10261/83167
DOI10.1109/TCSI.2010.2078851
ISSN1549-8328
Appears in Collections:(IMSE-CNM) Artículos
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