Flexible nanometer CMOS low-noise amplifiers for the next generation software-defined-radio mobile systems

Abstract

This chapter reviews the main circuit strategies reported so far for the implementation of reconfigurable and adaptive CMOS Low-Noise Amplifiers (LNAs) intended for multi-standard wireless telecom systems. Different performance metrics are analyzed and compared, and a number of practical design considerations are given in order to optimize the performance of these kinds of LNAs in terms of Noise Figure (NF) and S-parameter programmability, with scalable power consumption. To this purpose, a circuit design methodology is presented which combines a mathematical model with electrical simulations. As an application of the proposed design methodology, a LNA Integrated Circuit (IC) implemented in a 1-V 90-nm CMOS technology is presented. The circuit consists of a two-stage inductively degenerated common-source configuration and uses MOS-varactor based tunning networks to make the resonant frequency continuously programmable within the band of interest. This allows the LNA to target the requirements of a number of commercial licensed standards, as well as any other operation modes in between. Practical implementation issues are discussed, considering the effect of circuit parasitics associated to both the chip package and integrated inductors, capacitors, varactors, as well as technology parameter deviations. Experimental results are presented to demonstrate the correct operation of the IC, showing a continuous tuning of NF and S-parameters within a 1.75–2.48 GHz band, and featuring {NF} < 3. 7 {dB}, S 21 > 19. 6 {dB} and {IIP3} > − 9. 8 {dBm} in a frequency range of 1.75–2.23 GHz.