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dc.contributor.authorLéger, G.-
dc.contributor.authorRueda, Adoración-
dc.date.accessioned2012-12-03T14:27:57Z-
dc.date.available2012-12-03T14:27:57Z-
dc.date.issued2004-
dc.identifier.citationIEE Proceedings Circuits, Devices and Systems 151(4): 349–358 (2004)es_ES
dc.identifier.issn1350-2409-
dc.identifier.urihttp://hdl.handle.net/10261/61778-
dc.descriptionEl pdf del artículo es la versión post-print.-
dc.description.abstractThis paper proposes a digital technique to evaluate the integrator leakage within 1st and 2nd order ΣΔ modulators. Integrator leakage is known to be related to the converter precision and belongs to the basic set of design specifications. The technique proposed here involves very few hardware, which makes it specially suitable for Built-In Self-Test (BIST) implementation. Moreover, the integrator leakage evaluation allows its digital correction in cascaded modulators.es_ES
dc.language.isoenges_ES
dc.publisherInstitute of Electrical and Electronics Engineerses_ES
dc.relation.isversionofPostprint-
dc.rightsopenAccesses_ES
dc.titleDigital test for the extraction of integrator leakage in first- and second-order ΣΔ modulatorses_ES
dc.typeartículoes_ES
dc.identifier.doi10.1049/ip-cds:20040558(410)151-
dc.description.peerreviewedPeer reviewedes_ES
dc.relation.publisherversionhttp://dx.doi.org/10.1049/ip-cds:20040558(410)%20151es_ES
Appears in Collections:(IMSE-CNM) Artículos
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