English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/61778
Title: Digital test for the extraction of integrator leakage in first- and second-order ΣΔ modulators
Authors: Léger, G.; Rueda, Adoración
Issue Date: 2004
Publisher: Institute of Electrical and Electronics Engineers
Citation: IEE Proceedings Circuits, Devices and Systems 151(4): 349–358 (2004)
Abstract: This paper proposes a digital technique to evaluate the integrator leakage within 1st and 2nd order ΣΔ modulators. Integrator leakage is known to be related to the converter precision and belongs to the basic set of design specifications. The technique proposed here involves very few hardware, which makes it specially suitable for Built-In Self-Test (BIST) implementation. Moreover, the integrator leakage evaluation allows its digital correction in cascaded modulators.
Description: El pdf del artículo es la versión post-print.
Publisher version (URL): http://dx.doi.org/10.1049/ip-cds:20040558(410)%20151
URI: http://hdl.handle.net/10261/61778
ISSN: 1350-2409
DOI: 10.1049/ip-cds:20040558(410)151
Appears in Collections:(IMS-CNM) Artículos
Files in This Item:
File Description SizeFormat 
IEEspec_postprint.pdf2,91 MBAdobe PDFView/Open
Show full item record

WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.