English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/52639
Title: 1 V CMOS subthreshold log domain PDM
Authors: Serra-Graells, Francisco; Huertas-Díaz, J. L.
Keywords: Low voltage
Issue Date: 2003
Publisher: Springer
Citation: Analog Integrated Circuits and Signal Processing 34(3): 183-187 (2003)
Abstract: A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing through the MOSFET operating in weak inversion. A 1 V VLSI PDM circuit for very low-voltage audio applications such as Hearing Aids is presented, showing good agreement between simulated and experimental data.
Publisher version (URL): http://dx.doi.org/10.1023/A:1022545414777
URI: http://hdl.handle.net/10261/52639
ISSN: 0925-1030
DOI: 10.1023/A:1022545414777
E-ISSN: 1573-1979
Appears in Collections:(IMB-CNM) Artículos
(IMS-CNM) Artículos
Files in This Item:
File Description SizeFormat 
accesoRestringido.pdf15,38 kBAdobe PDFThumbnail
Show full item record

WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.