Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/52639
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Título : 1 V CMOS subthreshold log domain PDM
Autor : Serra-Graells, Francisco, Huertas-Díaz, J. L.
Palabras clave : Low voltage
CMOS
Subthreshold
Log
PDM
Fecha de publicación : 2003
Editor: Springer
Resumen: A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing through the MOSFET operating in weak inversion. A 1 V VLSI PDM circuit for very low-voltage audio applications such as Hearing Aids is presented, showing good agreement between simulated and experimental data.
Versión del editor: http://dx.doi.org/10.1023/A:1022545414777
URI : http://hdl.handle.net/10261/52639
ISSN: 0925-1030
DOI: 10.1023/A:1022545414777
Citación : Analog Integrated Circuits and Signal Processing 34(3): 183-187 (2003)
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