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Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/48219
Title: Low-power die-level process variation and temperature monitors for yield analysis and optimization in deep-submicron CMOS
Authors: Zjajo, Amir; Barragán, Manuel J. ; Pineda de Gyvez, José
Keywords: Analog test
Process variation monitoring
Temperature monitors
Yield enhancement
Issue Date: 6-Feb-2012
Publisher: Institute of Electrical and Electronics Engineers
Citation: IEEE Transactions on Instrumentation and Measurement 61(8): 2212-2221 (2012)
Abstract: This paper reports design, efficiency, and measure- ment results of the process variation and temperature monitors for yield analysis and enhancement in deep-submicron CMOS circuits. Additionally, to guide the verification process with the information obtained through monitoring, two efficient algorithms based on an expectation–maximization method and adjusted support vector machine classifier are proposed. The monitors and algorithms are evaluated on a prototype 12-bit analog-to- digital converter fabricated in standard single poly six-metal 90-nm CMOS.
Publisher version (URL): http://dx.doi.org/10.1109/TIM.2012.2184195
URI: http://hdl.handle.net/10261/48219
DOI: 10.1109/TIM.2012.2184195
ISSN: 0018-9456
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