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Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/3791
Title: A 0.35μm CMOS 17-bit@40kS/s Sensor A/D Interface Based on a Programmable-Gain Cascade 2-1 ΣΔ Modulator
Authors: García-González, José Manuel; Escalera, Sara; Rosa, José M. de la; Guerra, Oscar; Medeiro, Fernando; Río, Rocío del; Pérez-Verdú, Belén; Rodríguez-Vázquez, Ángel
Keywords: Sigma-Delta Modulator
Sensor Interface
Analog-to-Digital Converters
Issue Date: May-2004
Publisher: Institute of Electrical and Electronics Engineers
Citation: S. Escalera, J.M. García-González, J.M. de la Rosa, O. Guerra, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez: "A 0.35μm CMOS 17-bit@40kS/s Sensor A/D Interface Based on a Programmable-Gain Cascade 2-1 ΣΔ Modulator". Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS), pp. I.205-I.208, Vancouver, May 2004.
Abstract: This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a 0.35μm standard CMOS technology. The circuit is composed of a low-noise instrumentation preamplifier and a SC cascade (2-1) ΣΔ modulator. The preamplifier, based on hybrid Nested-Miller compensated four-stage opamps, has a fixed gain of 10 and it is capable of handling signals with 20kHz-bandwidth and amplitudes ranging from μVs to hundreds of mVs with a signal-to-(noise+distortion) ratio over 100dB. The modulator architecture has a programmable gain for a better fitting to the characteristics of different sensor outputs. The design of both circuits is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the interface hierarchy. Simulation results show 17-bit@40kS/s for all cases of the modulator gain.
URI: http://hdl.handle.net/10261/3791
References: 0-7803-8251-X/04
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