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Título: | Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology |
Autor: | Medeiro, Fernando CSIC; Pérez-Verdú, Belén CSIC; Rosa, José M. de la CSIC ORCID; Rodríguez-Vázquez, Ángel CSIC ORCID | Palabras clave: | Mixed-signal circuits Data conversion ΣΔM Optimized design CAD tools |
Fecha de publicación: | 1997 | Editor: | Wiley-Blackwell | Citación: | Journal Circuit Theory Applications 25(5): 319-334 (1997) | Resumen: | This paper uses a CAD methodology proposed by the authors to design a low-power 2nd-order Sigma-Delta Modulator (ΣΔM). This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16.4 bit at a digital output rate of 9.6 kHz with a power consumption of 1.7 mW. It yields a value of Power(W)/[2^resolution(bit) * Outpur rate(Hz)] which is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable ΣΔMs using CAD methodologies. | Descripción: | El pdf del artículo es la versión post-print. | Versión del editor: | http://dx.doi.org/10.1002/(SICI)1097-007X(199709/10)25:5<319::AID-CTA976>3.0.CO;2-U | URI: | http://hdl.handle.net/10261/3744 | DOI: | 10.1002/(SICI)1097-007X(199709/10)25:5<319::AID-CTA976>3.0.CO;2-U | ISSN: | 0098-9886 | E-ISSN: | 1097-007X |
Aparece en las colecciones: | (IMSE-CNM) Artículos |
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JCTA97_postprint.pdf | 1,6 MB | Adobe PDF | Visualizar/Abrir |
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