High-Order Cascade Multi-bit ΣΔ Modulators for High-Speed A/D Conversion

Por favor, use este identificador para citar o enlazar a este item: http://hdl.handle.net/10261/3598

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Título:	High-Order Cascade Multi-bit ΣΔ Modulators for High-Speed A/D Conversion
Autor:	Río, Rocío del CSIC ORCID; Medeiro, Fernando CSIC; Pérez-Verdú, Belén CSIC; Rodríguez-Vázquez, Ángel CSIC ORCID
Palabras clave:	ΣΔ Modulator A/D Conversion Communication Frequency Range
Fecha de publicación:	nov-1998
Editor:	Universidad Carlos III de Madrid
Citación:	Proc. Design of Circuits and Integrated Systems Conf. (DCIS’98), pp. 76-81, Madrid, November 1998.
Resumen:	The use of Sigma-Delta (ΣΔ) modulation for analog-to-digital conversion (ADC) in the communication frequency range is evaluated. Two high-order multi-bit architectures are proposed to achieve +12-bit dynamic range at 4Msample/s Nyquist rate using very low oversampling ratio. They show very low sensitivity to the internal D-to-A conversion (DAC) error with no calibration required. Simulations show that such performance can be achieved even in presence of circuit imperfections.
URI:	http://hdl.handle.net/10261/3598
Aparece en las colecciones:	(IMSE-CNM) Comunicaciones congresos