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Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/3598
Title: High-Order Cascade Multi-bit ΣΔ Modulators for High-Speed A/D Conversion
Authors: Río, Rocío del; Medeiro, Fernando ; Pérez-Verdú, Belén ; Rodríguez-Vázquez, Ángel
Keywords: ΣΔ Modulator
A/D Conversion
Communication Frequency Range
Issue Date: Nov-1998
Publisher: Universidad Carlos III de Madrid
Citation: Proc. Design of Circuits and Integrated Systems Conf. (DCIS’98), pp. 76-81, Madrid, November 1998.
Abstract: The use of Sigma-Delta (ΣΔ) modulation for analog-to-digital conversion (ADC) in the communication frequency range is evaluated. Two high-order multi-bit architectures are proposed to achieve +12-bit dynamic range at 4Msample/s Nyquist rate using very low oversampling ratio. They show very low sensitivity to the internal D-to-A conversion (DAC) error with no calibration required. Simulations show that such performance can be achieved even in presence of circuit imperfections.
URI: http://hdl.handle.net/10261/3598
Appears in Collections:(IMS-CNM) Comunicaciones congresos
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