English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/3597
Share/Impact:
Statistics
logo share SHARE   Add this article to your Mendeley library MendeleyBASE
Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:

Title

A 74dB Dynamic Range, 1.1-MHz Signal Band 4th-Order 2-1-1 Cascade Multi-Bit CMOS ΣΔ Modulator for ADSL

AuthorsMedeiro, Fernando ; Pérez-Verdú, Belén ; Rodríguez-Vázquez, Ángel
KeywordsΣΔ Modulator
A/D Conversion
CMOS A/D Converter
Issue DateSep-1997
CitationEuropean Solid-State Circuits Conference (ESSCIRC’97), pp. 72-75, Southampton - UK, September 16-18, 1997.
AbstractThis paper explores the use of ΣΔ techniques for A/D conversion exceeding 1-MHz signal bandwidth. A cascade modulator architecture is proposed which combines single-bit and multi-bit quantization to obtain more than 12-b Dynamic Range (DR) with an oversampling ratio of only 16, and with neither calibration nor trimming required. Measurements from a 0.7mm CMOS prototype show 74dB DR in 1.1-MHz signal band at 35.7-MHz clock rate, with a power consumption of 55mW from a 5-V supply.
URIhttp://hdl.handle.net/10261/3597
Appears in Collections:(IMSE-CNM) Comunicaciones congresos
Files in This Item:
File Description SizeFormat 
Dynamic_range.pdf103,83 kBAdobe PDFThumbnail
View/Open
Show full item record
Review this work
 


WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.