English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/228099
Share/Impact:
Statistics
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL | DATACITE
Exportar a otros formatos:

Title

A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

AuthorsParsakordasiabi, Mojtaba; Vornicu, Ion; Rodríguez-Vázquez, Ángel ; Carmona-Galán. R.
KeywordsField programmable gate array (FPGA)
Tapped-delay-line (TDL)
Thermometer-to-binary (T2B) encoder
Multichannel TDCs
Time-to-digital converter (TDC)
Time-of-flight (ToF)
Singlephoton avalanche diode (SPAD)
Issue Date2021
PublisherMDPI
CitationSensors, 21: 308 (2021)
AbstractIn this paper, we present a proposed field programmable gate array (FPGA)-based timeto- digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [􀀀0.953, 1.185] LSB, and an integral non-linearity (INL) within [􀀀2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.
Publisher version (URL)https://doi.org/10.3390/s21010308
URIhttp://hdl.handle.net/10261/228099
DOI10.3390/s21010308
Appears in Collections:(IMSE-CNM) Artículos
Files in This Item:
File Description SizeFormat 
sensors-21-00308-v2.pdf5,32 MBAdobe PDFThumbnail
View/Open
Show full item record
Review this work
 


WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.