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dc.contributor.authorLópez-Martínez, Juan Manueles_ES
dc.contributor.authorCarmona-Galán, R.es_ES
dc.contributor.authorRodríguez-Vázquez, Ángeles_ES
dc.date.accessioned2021-01-20T10:33:20Z-
dc.date.available2021-01-20T10:33:20Z-
dc.date.issued2020-
dc.identifier.citationIEEE International Symposium on Circuits and Systems (ISCAS). 2020es_ES
dc.identifier.urihttp://hdl.handle.net/10261/227130-
dc.description.abstractSingle-photon avalanche diodes can be employed to register the arrival of an individual photon. They are biased beyond breakdown voltage, and thus the electron-hole pairs generated by any incident photon is accelerated by the strong electric field triggering an avalanche current. In recent years, there have been attempts to model its characteristics in Verilog-A HDL. However, none of them have modelled its photon-detection timing jitter. This paper explains the mechanism of avalanche triggering and proposes a first approach to model it in Verilog-A. Comparison with experimental data and data reported in literature validates the model.es_ES
dc.language.isoenges_ES
dc.publisherInstitute of Electrical and Electronics Engineerses_ES
dc.relation.isversionofPostprintes_ES
dc.rightsopenAccesses_ES
dc.subjectPhotonicses_ES
dc.subjectElectric fieldses_ES
dc.subjecttiming jittees_ES
dc.subjectVerilog-Aes_ES
dc.subjectSingle-photon avalanche diode (SPAD)es_ES
dc.subjectDevice simulationes_ES
dc.titlePhoton-Detection Timing-Jitter Model in Verilog-Aes_ES
dc.typecomunicación de congresoes_ES
dc.identifier.doi10.1109/ISCAS45731.2020.9181222-
dc.description.peerreviewedPeer reviewedes_ES
dc.relation.publisherversionhttps://doi.org/10.1109/ISCAS45731.2020.9181222es_ES
dc.relation.csices_ES
oprm.item.hasRevisionno ko 0 false*
dc.type.coarhttp://purl.org/coar/resource_type/c_5794es_ES
item.languageiso639-1en-
item.fulltextWith Fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.cerifentitytypePublications-
item.grantfulltextopen-
item.openairetypecomunicación de congreso-
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