English   español  
Please use this identifier to cite or link to this item: http://hdl.handle.net/10261/180442
Share/Impact:
Statistics
logo share SHARE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:

Title

All-inversion region gm/ID methodology for RF circuits in FinFET technologies

AuthorsFiorelli, R. ; Núñez, Juan ; Silveira, Fernando
KeywordsFinFETs
Capacitance
Radio frequency
Inductors
Phase noise
Issue Date2018
PublisherInstitute of Electrical and Electronics Engineers
Citation16th IEEE International New Circuits and Systems Conference (NEWCAS). 2018
AbstractIn the context of IoT applications, together with the use of deep-submicron technologies as FinFET, this paper presents a revision of the gm/ID methodology for radio-frequency analog front-end circuits. Particularly, this methodology is applied for the design of LC-VCOs in the 5.8-GHz band using 20-nm FinFET transistors. To incorporate the FinFET model into the design flow, a semi-empirical model is extracted from electrical simulations. To show the good performance of the methodology, an LC-VCO design, picked from the calculated design maps, is electrically simulated, achieving good match regarding oscillation frequency and phase noise.
Publisher version (URL)https://doi.org/10.1109/NEWCAS.2018.8585627
URIhttp://hdl.handle.net/10261/180442
DOI10.1109/NEWCAS.2018.8585627
Appears in Collections:(IMSE-CNM) Comunicaciones congresos
Files in This Item:
File Description SizeFormat 
C2.pdf179,65 kBAdobe PDFThumbnail
View/Open
Show full item record
Review this work
 


WARNING: Items in Digital.CSIC are protected by copyright, with all rights reserved, unless otherwise indicated.