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Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines

AuthorsQuintero, Héctor J.; Jiménez, M.; Avedillo, M. J. ; Núñez, Juan
Issue Date2-Jul-2018
PublisherInstitute of Electrical and Electronics Engineers
Citation 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
AbstractVery fine grained latch-free pipelines are successfully used in critical parts of high performance systems. These approaches are based in Domino logic and multi-phase clock schemes. Reducing the number of logic levels per clock phase and the number of phases to the minimum is a potential way to push the limits of speed. However the implementation of such architectures with just one logic level per clock phase and two clock phases is a challenge which requires extremely full-custom design and exhibits robustness concerns. In this paper we show that the non-inverting feature of Domino plays a critical role in these difficulties. We analyze and compare the performance of two-phase gate-level pipelines implemented with Domino and with ILP, an inverting dynamic gate we have proposed. Our experiments confirm that ILP pipelines are much more robust and could simplify design.
Identifiersdoi: 10.1109/SMACD.2018.8434921
Appears in Collections:(IMSE-CNM) Comunicaciones congresos
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