English   español  
Por favor, use este identificador para citar o enlazar a este item: http://hdl.handle.net/10261/171863
COMPARTIR / IMPACTO:
Estadísticas
logo share SHARE logo core CORE   Add this article to your Mendeley library MendeleyBASE

Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar a otros formatos:
Título

On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights

AutorYousefzadeh, Amirreza; Stromatias, Evangelos; Soto, Miguel; Serrano-Gotarredona, Teresa ; Linares-Barranco, Bernabé
Palabras claveSpiking neural networks
Spike timing dependent plasticity
Stochastic learning
Feature extraction
Neuromorphic systems
Fecha de publicación2018
EditorFrontiers in Bioscience Publications
CitaciónFrontiers in Neuroscience, 12: 665 (2018)
ResumenIn computational neuroscience, synaptic plasticity learning rules are typically studied using the full 64-bit floating point precision computers provide. However, for dedicated hardware implementations, the precision used not only penalizes directly the required memory resources, but also the computing, communication, and energy resources. When it comes to hardware engineering, a key question is always to find the minimum number of necessary bits to keep the neurocomputational system working satisfactorily. Here we present some techniques and results obtained when limiting synaptic weights to 1-bit precision, applied to a Spike-Timing-Dependent-Plasticity (STDP) learning rule in Spiking Neural Networks (SNN). We first illustrate the 1-bit synapses STDP operation by replicating a classical biological experiment on visual orientation tuning, using a simple four neuron setup. After this, we apply 1-bit STDP learning to the hidden feature extraction layer of a 2-layer system, where for the second (and output) layer we use already reported SNN classifiers. The systems are tested on two spiking datasets: a Dynamic Vision Sensor (DVS) recorded poker card symbols dataset and a Poisson-distributed spike representation MNIST dataset version. Tests are performed using the in-house MegaSim event-driven behavioral simulator and by implementing the systems on FPGA (Field Programmable Gate Array) hardware
Versión del editorhttps://doi.org/10.3389/fnins.2018.00665
URIhttp://hdl.handle.net/10261/171863
DOI10.3389/fnins.2018.00665
Aparece en las colecciones: (IMSE-CNM) Artículos
Ficheros en este ítem:
Fichero Descripción Tamaño Formato  
fnins-12-00665.pdf6,65 MBAdobe PDFVista previa
Visualizar/Abrir
Mostrar el registro completo
 


NOTA: Los ítems de Digital.CSIC están protegidos por copyright, con todos los derechos reservados, a menos que se indique lo contrario.