English   español  
Por favor, use este identificador para citar o enlazar a este item: http://hdl.handle.net/10261/156345
Compartir / Impacto:
Estadísticas
Add this article to your Mendeley library MendeleyBASE
 |  Ver citas en Google académico
Visualizar otros formatos: MARC | Dublin Core | RDF | ORE | MODS | METS | DIDL
Exportar otros formatos: Exportar EndNote (RIS)Exportar bibText (RIS)Exportar csv (RIS)
Título

On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems

Autor Yousefzadeh, Amirreza; Jabłonski, M.; Iakymchuk, T.; Linares-Barranco, Alejandro; Rosado, Alfredo; Plana, Luis A.; Temple, Steve; Serrano-Gotarredona, Teresa ; Furber, Steve B.; Linares-Barranco, Bernabé
Fecha de publicación 2017
EditorInstitute of Electrical and Electronics Engineers
Citación IEEE Transactions on Biomedical Circuits and Systems, 11(5): 1133-1147 (2017)
ResumenAddress event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available.
Versión del editorhttps://doi.org/10.1109/TBCAS.2017.2717341
URI http://hdl.handle.net/10261/156345
DOI10.1109/TBCAS.2017.2717341
Aparece en las colecciones: (IMSE-CNM) Artículos
Ficheros en este ítem:
Fichero Descripción Tamaño Formato  
08010303.pdf4,24 MBAdobe PDFVista previa
Visualizar/Abrir
Mostrar el registro completo
 


NOTA: Los ítems de Digital.CSIC están protegidos por copyright, con todos los derechos reservados, a menos que se indique lo contrario.