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Título

Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements

Autor Núñez, Juan ; Avedillo, M. J. ; Quintana, Héctor J.
Palabras clave Monostable-to-Bistable Logic Element
Negative Differential Resistance
Pipeline
Clock schemes
Fecha de publicación 2014
EditorInstitute of Electrical and Electronics Engineers
Citación IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 22(10): 2238-2242 (2015)
ResumenAbstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without resorting to memory elements. The MOBILE operating principle is implemented operating two series connected negative differential resistance devices with a clock bias. This brief describes and experimentally validates a two-phase clock scheme for such MOBILE-based ultragrained pipelines. Its advantages over other reported interconnection schemes for MOBILE gates, and also over pure CMOS two-phase counterparts, are stated and analyzed. Chains of MOBILE gates have been fabricated and the experimental results of their correct operation with a two-phase clock scheme are provided. As far as we know, this is the first working MOBILE circuit to have been reported with this interconnection architecture.
Versión del editorhttps://doi.org/10.1109/TVLSI.2013.2283306
URI http://hdl.handle.net/10261/155916
DOI10.1109/TVLSI.2013.2283306
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