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Título

Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas

Autor Núñez, Juan ; Avedillo, M- J.
Palabras clave Tunnel transistors
Steep subthreshold slope
Low power
Energy efficieny
Low supply voltage
Fecha de publicación 2016
EditorInstitute of Electrical and Electronics Engineers
Citación IEEE Journal of the Electron Devices, 63(12): 5012-5020 (2016)
ResumenIn this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas.
Versión del editorhttps://doi.org/10.1109/TED.2016.2616891
URI http://hdl.handle.net/10261/155915
DOI10.1109/TED.2016.2616891
Aparece en las colecciones: (IMSE-CNM) Artículos
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