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Título

DOE based high-performance gate-level pipelines

Autor Núñez, Juan ; Avedillo, M. J. ; Quintero, Héctor J.
Palabras clave Nanopipeline
Dynamic logic
Robust design techniques
Fecha de publicación 2014
EditorInstitute of Electrical and Electronics Engineers
Citación Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014 24th International Workshop on, 29 Sept- 1 Oct. 2014
ResumenAbstract: Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in addition to the functional limitation associated to the non-inverting behavior of domino gates, there are also performance disadvantages when compared to inverting dynamic gates, which can be related to this feature. These penalties rise from the fact that in order to produce a logic one, a non-inverting gate requires one or more of its inputs to be also at logic one. We analyze the operation of gate-level pipelines implemented with domino and with Delayed Output Evaluation (DOE), an inverting dynamic gate we have recently proposed, and compare their performance. Using domino and DOE gates similar in terms of delay, improvements in operating frequencies around 50% have been obtained by the DOE pipelines.
Versión del editorhttps://doi.org/10.1109/PATMOS.2014.6951902
URI http://hdl.handle.net/10261/155911
DOI10.1109/PATMOS.2014.6951902
Aparece en las colecciones: (IMSE-CNM) Comunicaciones congresos
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