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Impact of pipeline in the power performance of tunnel transistor circuits

AutorAvedillo, M. J. ; Núñez, Juan
Palabras claveTunnel transistors
Steep subthreshold slope
Low power
Energy efficieny
Logic depth
Fecha de publicación2017
EditorInstitute of Electrical and Electronics Engineers
CitaciónPower and Timing Modeling, Optimization and Simulation (PATMOS), 2016 26th International Workshop on, 21-23 Sept. 2016
ResumenTunnel transistors are one of the most attractive steep sub threshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, we analyze the impact of the logic depth into the power consumption and energy efficiency of logic circuits and show critical differences between tunnel transistors and CMOS technologies, due to the distinct delay versus supply voltages exhibited by each type of device. Obtained results show that reducing logic depth as a power reduction technique is more efficient for tunnel transistors circuits than for their CMOS counterparts. A simple model to estimate the power reductions achieved when using pipeline to cut down logic depth, and taking into account the power overheads associated to the pipelined registers is developed. It shows that in CMOS power benefits cancels with the incorporation of a number of flip-flops equal to the 5% of the number of gates in the original circuit while this number rises to 90% for tunnel circuits. Simulation experiments of a simple adder tree are carried out to validate our analysis. No power savings are obtained by the CMOS pipelined circuit while the TFET pipelined circuit saves 77% of power. The results of this work suggest that architectural issues should be considered in the evaluation of this type of transistors.
Versión del editorhttps://doi.org/10.1109/PATMOS.2016.7833696
Aparece en las colecciones: (IMSE-CNM) Comunicaciones congresos
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