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Título

Exploring logic architectures suitable for TFETs devices

Autor Núñez, Juan ; Avedillo, M. J.
Palabras clave Tunnel transistors
Steep subthreshold slope
Low power
Low supply voltage
Fine-grained pipeline
Fecha de publicación 2017
EditorInstitute of Electrical and Electronics Engineers
Citación IEEE International Symposium on Circuits and Systems ISCAS 2017 conference.
ResumenTunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates to overcome the power density and energy inefficiency limitations of CMOS technology, which are critical for IoT development. Although they show higher ON currents than CMOS at low supply voltages, currently TFETs do not reach those exhibited by CMOS at its nominal supply voltage and so they have being identified to be competitive for moderate operating frequencies. However, in many cases, architectural choices are not taken into account when benchmarking them against CMOS. In this paper we claim that the logic architecture should be selected in order to take full advantage of the specific characteristics of these devices. Widely used circuits are designed and evaluated showing how properly tuning the logic architecture results in raising the frequency up to which TFETs are competitive or in increasing power savings at lower frequencies.
URI http://hdl.handle.net/10261/155909
Aparece en las colecciones: (IMSE-CNM) Comunicaciones congresos
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