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Insights Into the Operation of Hyper-FET-Based Circuits

Autor Avedillo, M. J. ; Núñez, Juan
Palabras clave Steep subthreshold slope
Phase transition materials
Low power
Low voltage
Energy effiency
Fecha de publicación 2017
EditorInstitute of Electrical and Electronics Engineers
Citación IEEE Journal of the Electron Devices, 64(9): 3912-3918 (2017)
ResumenAbstract: Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the ION/IOFF ratio and, thus, to solve power and energy limitations of CMOS technologies. This paper analyzes the operation of circuits built with these devices. In particular, we use a recently projected device called hyper-FET to simulate different circuits, and to analyze the impact of the degraded dc output voltage levels of hyper-FET logic gates on their circuit operation. Experiments have been carried out to evaluate power of these circuits and to compare with counterpart circuits using FinFETs. The estimated power advantages from device level analysis are also compared with the results of circuit level measurements.We show that these estimation scan reduce, cancel, or even lead to power penalties in low switching and/or low-frequency circuits. We also discuss relationships with some device level parameters showing that circuit level considerations should be taken into account for device design
Versión del editorhttps://doi.org/10.1109/TED.2017.2726765
URI http://hdl.handle.net/10261/155907
Aparece en las colecciones: (IMSE-CNM) Artículos
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