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Improving speed of tunnel FETs logic circuits

AutorAvedillo, J. M.; Núñez, Juan
Fecha de publicación2015
EditorInstitute of Electrical and Electronics Engineers
CitaciónElectronics Letters, 51(21): 1702-1704 (2015)
ResumenTunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigating to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit asymmetric conduction which can cause sustained noise voltage pulses (bootstrapping) within digital TFETs circuits leading to delay degradation. In this paper, we propose a minor modification of the complementary gate topology to avoid the bootstrapping problem and show its impact on speed at the circuit level. Speed improvements up to 33% have been obtained for 8-bit Ripple Carry Adders when implemented with our solution.
Versión del editorhttps://doi.org/10.1049/el.2015.2416
URIhttp://hdl.handle.net/10261/155904
DOI10.1049/el.2015.2416
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