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Título : Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
Autor : Núñez, Juan ; Avedillo, M. J.
Palabras clave : Tunnel transistors
Steep subthreshold slope
Energy efficiency,
Low supply voltage
Optimal design points
Fecha de publicación : 2017
Editor: Institute of Electrical and Electronics Engineers
Citación : IEEE Transactions on Nanotechnology, 16(1): 83-89 (2017)
Resumen: Abstract: Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct fan-in logic gates, using a set of widely accepted power-speed metrics, are addressed for five projected tunnel transistor (TFET) technologies and four mosfet and FinFET transistors. The impact of logic depth, switching activity, and minimum supply voltage has been also included in our analysis. Provided results suggest that benefits in terms of a certain metric, in which a higher weight is placed on power or delay, are strongly determined by the selected device. Particularly, the suitability of two of the explored TFET technologies to improve CMOS performance for different metrics is pointed out. A circuit level benchmark is evaluated to validate our analysis.
Versión del editor: https://doi.org/10.1109/TNANO.2016.2629264
URI : http://hdl.handle.net/10261/146905
DOI: 10.1109/TNANO.2016.2629264
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