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dc.contributor.authorCarmona-Galán, R.es_ES
dc.contributor.authorFernández-Berni, J.es_ES
dc.contributor.authorRodríguez-Vázquez, Ángeles_ES
dc.identifier.citationInternational Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Dresden, Germany, in August 2016es_ES
dc.descriptionThe 15th International Workshop on Cellular Nanoscale Networks and their Applications will be held on August 23-25, 2016 in the city of Dresden, Germany.es_ES
dc.description.abstractSpeeding up algorithm execution can be achieved by increasing the number of processing cores working in parallel. Of course, this speedup is limited by the degree to which the algorithm can be parallelized. Equivalently, by lowering the operating frequency of the elementary processors, the algorithm can be realized in the same amount of time but with measurable power savings. An additional result of parallelization is that using a larger number of processors results in a more efficient implementation in terms of GOPS/W. We have found experimental evidence for this in the study of massively parallel array processors, mainly dedicated to image processing. Their distributed architecture reduces the energy overhead dedicated to data handling, thus resulting in a power efficient implementationes_ES
dc.publisherInstitute of Electrical and Electronics Engineerses_ES
dc.subjectParallel processinges_ES
dc.subjectCellular Processing Arrayes_ES
dc.subjectMulticore processinges_ES
dc.subjectComputational efficiencyes_ES
dc.titleExperimental Evidence of Power Efficiency due to Architecture in Cellular Processor Array Chipses_ES
dc.typecomunicación de congresoes_ES
dc.description.peerreviewedPeer reviewedes_ES
oprm.item.hasRevisionno ko 0 false*
Appears in Collections:(IMSE-CNM) Comunicaciones congresos
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