Mixed-Signal Techniques for Robust Auto-Tuning of Split-Tuned PLL Frequency Synthesizers

Abstract

This paper proposes two different phase-locked loop (PLL) auto-tuning techniques for low-cost sub-band selec-tion in split-tuned frequency synthesizers. The methods conti-nuously monitor the tuning voltage Vtune of the voltage-controlled oscillator (VCO) using two comparators whose threshold voltages define the PLL design region. Considering the comparators deci-sion, a simple digital control unit (DCU) generates a correction signal which assures Vtune is always within the allowable range, hence concurrently dealing with process, voltage and tempera-ture (PVT) variations. Two alternative algorithms depending on the DCU implementation have been proposed as trade-off between hardware complexity and convergence response. Both algorithms have been experimentally validated in a 1.2V PLL frequency synthesizer. This PLL block is part of a monolithical 2.4GHz IEEE 802.15.4 ZigBee transceiver implemented in a RF 90nm CMOS technology.