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Improving delay-noise trade-off of dynamic gates for fine-grained pipelined applications

AutorNúñez, Juan ; Avedillo, M. J. ; Quintana, J. M. ; Quintero, Héctor
Fecha de publicación2013
EditorInstitute of Electrical and Electronics Engineers
CitaciónConference on the Design of Circuits and Integrated Systems DCIS 2013
ResumenDynamic logic is well suited to implement very fine-grained pipelining for high performance functional units and has been successfully applied in commercial applications. Technology scaling and current increasing frequency targets have augmented the main problems exhibited by conventional dynamic gates topologies: larger leakage and coupling leading to higher noise susceptibility, logic design constrained by their functional limitation, being able to implement only non inverting functions and the labor-intensive design required due to timing challenges of fine grained pipelines used for high through-output. Development of novel topologies aiming to cope with all these challenges is an area of active research. In this paper, we describe a novel topology that addresses all the above stated problems. The proposed gate implements inverting functionalities, exhibits very competitive delay-noise tradeoffs and it is well suited to implement building blocks with function-independent delays which can simplify design. Unlike previous reported solutions, it is the gate static output stage which is modified. The novel topology is analyzed and evaluated, and a gate per phase Carry Look Ahead adder is designed as an application example.
Aparece en las colecciones: (IMSE-CNM) Comunicaciones congresos
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