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Título

A 176x120 Pixel CMOS Vision Chip for Gaussian Filtering with Massivelly Parallel CDS and A/D-Conversion

AutorSuárez, Marta ; Brea, V. M.; Cabello, Cecilia; Fernández-Berni, J. ; Carmona-Galán, R. ; Rodríguez-Vázquez, Ángel
Fecha de publicación2013
EditorInstitute of Electrical and Electronics Engineers
CitaciónEuropean Conference on Circuit Theory and Desing (ECCTD), 2013 : 1-4
ResumenThis paper conveys a proof-of-concept chip for Gaussian pyramid generation for image feature detectors. Gaussian filtering and image resizing are performed with a switched-capacitor (SC) network. The chip is conceived as the mapping of a CMOS-3D architecture for feature detectors onto a conventional technology, with some functionality removed, and the corresponding area overhead with respect to that of a CMOS-3D architecture, but preserving masivelly parallel Correlated Double Sampling (CDS) and A/D conversion. The chip has been fabricated on a die of 5×5 mm2 with 0.18 ¿m CMOS technology, achieving an array of 176×120 sensing elements (pixels). The pixels are arranged in Processing Elements (PEs). Every PE comprises four photodiodes, four SC nodes, one CDS circuit, and local circuitry for one ADC. Every PE occupies an area of 44×44 ¿m2. The chip senses an image and computes the Gaussian pyramid with an average power consumption lower than 75 nW/pixel at 30 frames/s.
URIhttp://hdl.handle.net/10261/104728
DOI10.1109/ECCTD.2013.6662293
Identificadoresdoi: 10.1109/ECCTD.2013.6662293
Aparece en las colecciones: (IMSE-CNM) Comunicaciones congresos
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